Method for manufacturing nonvolatile semiconductor memory with narrow variation in threshold voltages of memory cells

ABSTRACT

In a method for manufacturing a memory cell of a nonvolatile semiconductor memory, a floating gate, first insulating film and control gate are successively stacked on a tunnel oxide film formed on a substrate of the nonvolatile semiconductor memory. The control gate, the first insulating film and the floating gate are patterned in stripes. Subsequently, a damaged portion of the tunnel oxide film immediately below a sidewall of the floating gate is removed by isotropic etching. A second insulating film is deposited to cover the control gate, sidewalls of the first insulating film, the floating gate and the tunnel oxide film. Thereby, a variation in threshold voltages between memory cells is suppressed.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a method for manufacturing anonvolatile semiconductor memory. More specifically, the presentinvention relates to a method for manufacturing a nonvolatilesemiconductor memory having a tunnel oxide film, floating gate,insulating film and control gate stacked in this order on asemiconductor substrate.

[0002] Conventionally, a nonvolatile semiconductor memory of this kindis manufactured according to a process order shown in FIGS. 10A to 10Band 11A to 11C. FIGS. 10A to 10C are cross sections in an X-X directionin FIG. 1A. FIGS. 11A to 11C are cross sections in a Y-Y direction inFIG. 1A. Here, FIG. 1A is a plan view of a nonvolatile semiconductormemory according to an embodiment of the present invention, but FIG. 1Ais also used to explain a conventional technique.

[0003] First, as shown in FIGS. 11A and 11A, a tunnel oxide film 2having a thickness of 10 nm is formed on a semiconductor substrate 1 bythermal oxidation. Then, a first conductive layer 3 having a thicknessof 100 nm is deposited. The first conductive layer 3 is composed ofpolysilicon as a material of a floating gate. Subsequently, the tunneloxide film 2 and the first conductive layer 3 are patterned in stripesextending in the Y-Y direction At this time, a size of the firstconductive layer 3 in the X-X direction (channel direction) is set so asto match a size of the floating gate to be finally formed.

[0004] Subsequently, phosphorus (P) ion implantation is performed underconditions of an acceleration energy of 50 keV and a dose of 3.0×10¹³ions/cm² by using the first conductive layer 3 patterned in stripes as amask so as to form an n-type low-concentration impurity diffusion layer4 in a surface region of the semiconductor substrate between fine firstconductive layers 3.

[0005] Subsequently, photolithography is performed to form a photoresist(not shown) in stripes extending in the Y-Y direction. Arsenic (As) ionimplantation is performed by using this photoresist and the firstconductive layer 3 patterned in stripes as masks under conditions of anacceleration energy 15 keV and a dose of 4.5×10¹⁵ ions/cm² so as to forman n-type high-concentration impurity diffusion layer 5 in thelow-concentration impurity diffusion layer 4. These impurity diffusionlayers 4, 5 are used as the a source/drain region i.e. a bit line.

[0006] Subsequently, as shown in FIG. 10B, an interlayer insulating film6 is deposited on these layers in a thickness exceeding the thickness ofthe first conductive layer 3 by the CVD method to sufficiently cover thefirst conductive layer 3. Subsequently, an etchback is performed toplanarize the surface of the interlayer insulating film 6, and theinterlayer insulating film 6 is so left as to be embedded between thefirst conductive layers 3.

[0007] Subsequently, as shown in FIGS. 10C and 11C, a first insulatingfilm 7 composed of, for example, an ONO film (oxide film/nitridefilm/oxide film) is deposited and then a second conductive layer 8composed of polysilicon having a thickness of 200 nm is deposited. Then,photolithography is performed to form a photoresist (not shown) instripes extending in the X-X direction. The second conductive layer 8,the first insulating film 7 and the first conductive layer 3 are etchesand patterned by using this photoresist as a mask. Consequently, thereare formed a control gate in stripes composed of the second conductivelayer 8, the first insulating film 7 in stripes composed of the ONO filmand a floating gate in a rectangular solid composed of the firstconductive layer 3.

[0008] In this state, as shown in FIG. 12A which is an enlarged view ofa portion P enclosed with a broken line in FIG. 11C, a portion of thetunnel oxide film 2 immediately below a sidewall of the floating gate 3includes damages (shown with x). This damaged portion easily serves as apath for electrons to leak from the floating gate 3 to the semiconductorsubstrate 1 side during an operation of a finished product. Accordingly,as shown in FIG. 12B, thermal oxidation is performed, for example, in anoxygen atmosphere at 850° C. for 20 minutes so as to form a siliconoxide film 11 having a thickness of 20 to 30 nm on the sidewalls of thefloating gate 3 composed of polysilicon and the control gate 8.

[0009] Subsequently, as shown in FIG. 11C, boron (B) ion implantation isperformed under conditions of an acceleration energy 40 keV and a doseof 1.0×10¹³ ions/cm² by using the control gate 8 as a mask so as to forma p-type element separating impurity diffusion layer 9 in a surfaceregion of the semiconductor substrate 1 between the control gates 8.

[0010] Then, an interlayer insulating film is deposited on this layer bya known method, a contact hole is opened in this interlayer insulatingfilm and then interconnect lines are further formed to complete anonvolatile memory, none of which are shown.

[0011] However, in the above conventional manufacturing method, as shownin FIG. 7 which is an enlarged view of a portion P1 enclosed with abroken fine in FIG. 12A, a grain boundary 13 between polysilicon grains12 of the floating gate 3 is easily oxidized during the process ofoxidizing the sidewalls of the floating gate 3 and the control gate 8because the silicon oxide film 11 is formed on the sidewalls of thefloating gate 3 and the control gate 8, resulting in localizednonuniform oxidation. As a result, a localized electric fieldconcentration occurs between the floating gate 3 and the source/drainregion in the semiconductor substrate 1 during an operation of thenonvolatile memory. Thus, a problem arises that equal FN(Fowler-Nordheim) currents do not flow through the tunnel oxide film ineach memory cell during a write operation, thereby increasing avariation in threshold voltages between the memory cells.

[0012] As known, usually, data is simultaneously written in memory cellson the same word line (control gate). As evident from FIG. 9 snowing athreshold voltage distribution after a write operation in memory cellson the same word line, there is a large variation of 2.2 V in thresholdvoltages among nonvolatile memory cells on the same word line, whichcells are manufactured by the above method.

[0013] In order to even the threshold voltages during a write operation,a verify write operation for each bit is usually performed. However,when there is a large variation in threshold voltages among memory cellson the same word line as described above, the number of steps during thewrite operation needs to be increased, resulting in a longer write time.

[0014] Furthermore, when data is written in this semiconductor memory, ahigh voltage is also applied to a nonselected memory cell on the sameword line. Therefore, electrons in a floating gate of the nonselectedcell are decreased (gate disturbance). When the variation in thresholdvoltages is large among memory cells on the same word line, a memorycell in which data can be particularly rapidly written is easilyaffected by the gate disturbance.

[0015] To solve the above problem, as shown in FIG. 13, a technique hasbeen proposed wherein a tunnel oxide film 24, a floating gate electrode25 and a source region 22 are formed on the semiconductor substrate 21,thereafter a material of the floating gate electrode 25 is isotropicallyetched and then oxidized (Japanese Patent Laid-Open PublicationH9-17890). With this technique, a corner portion of the floating gate 25on the semiconductor substrate 21 is made round while an oxide film 28is formed. However, this technique cannot control the localizednon-uniform oxidation attributable to polysilicon grains constitutingthe floating gate electrode 25. As a result, an electric fieldconcentration cannot be prevented and a variation in FN currents occursfor each memory cell and the variation in threshold voltages betweenmemory cells is increased. Furthermore, since controlling of an etchingrate in the isotropic etching process is difficult, a large margin isrequired, thereby hindering future miniaturization. Furthermore, thesize of the floating gate changes depending on the etching rate in theisotropic etching process and the channel length and the channel widthchange, which also causes a variation in threshold voltage.

SUMMARY OF THE INVENTION

[0016] Accordingly, an object of the present invention is to provide amethod for manufacturing a nonvolatile semiconductor memory by whichvarious problems such as gate disturbance can be solved by suppressingvariations in threshold voltages of the nonvolatile semiconductor.

[0017] To achieve the above object, the present invention provides amethod for manufacturing a nonvolatile semiconductor memory whereinmemory cells each having a tunnel oxide film, a floating gate, a firstinsulating film and a control gate stacked in this order are formed in amatrix on a semiconductor substrate, the method comprising the steps of:

[0018] forming the tunnel oxide film on the semiconductor substrate;

[0019] forming a first conductive layer to be used as a material of thefloating gate on the tunnel oxide film;

[0020] patterning the first conductive layer in stripes extending in onedirection;

[0021] forming a source/drain region in a surface of the semiconductorsubstrate by using the first conductive layer as a mask;

[0022] forming the first insulating film on the first conductive layer;

[0023] forming a second conductive layer on the first insulating film;

[0024] forming the control gate in stripes composed of the secondconductive layer, the first insulating firm in stripes and the floatinggate in a rectangular solid composed of the first conductive layer byetching with a mask in stripes extending a direction perpendicular tothe first conductive layer;

[0025] removing a portion of the tunnel oxide film immediately below asidewall of the floating gate by isotropical etching; and

[0026] depositing a second insulating film on the control gate,sidewalls of the first insulating film, the floating gate and the tunneloxide film to be covered with the second insulating film.

[0027] According to the present invention, a portion of the tunnel oxidefilm immediately below the sidewall of the floating gate is removed byisotropic etching. This removes a damaged layer generated in she tunneloxide film during the process of forming the floating gate. Therefore,there would be no path for electrons to leak from the floating gate tothe semiconductor substrate side during an operation of a finishedproduct. Furthermore, when the second insulating film is deposited andthen thermal oxidation is performed to oxidize the sidewall or thefloating gate via the second insulating film, uniform oxidation occursat an interface between the floating gate and the surrounding insulatingfilm. Therefore; equal FN (Fowler-Nordheim) currents flow through thetunnel oxide film in each memory cell during a write operation. Thus,compared with a conventional memory, the variation in threshold voltagesamong memory cells, for example, memory cells on the same word line isreduced.

[0028] As a result, since there is no variation in threshold voltages onthe same word line, the number of steps during the write operation canbe reduced, thereby shortening the write time.

[0029] In addition, since memory cells on the same word line whereindata is written particularly rapidly can be erased, the number of memorycells affected by gate disturbance can be reduced.

[0030] Furthermore, since the second insulating film is formed in aspace portion of the floating gate, miniaturization is not hindered.

[0031] Still furthermore, the size of the floating gate does not changedepending on isotropic etching of the tunnel oxide film after formationof the floating gate or deposition of the second insulating film.Therefore, there is no problem of a short channel effect due to thechannel length or a narrow channel effect due to the channel width andno variation in threshold voltages attributable to then occurs.

[0032] In one embodiment of the present invention, after the secondinsulating film is deposited, thermal oxidation is performed to oxidizethe sidewall of the floating gate via the second insulating film.

[0033] According to the embodiment, uniform oxidation occurs at aninterface between the floating gate and the surrounding insulating film.Therefore, equal FN (Fowler-Nordheim) currents flow through the tunneloxide film in each memory cell during a write operation. Thus, comparedwith a conventional memory, the variation in threshold voltages betweenmemory cells, for example, memory cells on the same word line isreduced.

[0034] In one embodiment of the present invention, isotropic etching ofthe tunnel oxide film after formation of the floating gate is performedby wet etching using a fluorinated acid.

[0035] According to the embodiment, a portion of the tunnel oxide filmimmediately below a sidewall of the floating gate can be preciselyremoved by wet etching using the fluorinated acid.

[0036] In one embodiment of the present invention, the second insulatingfilm is a silicon oxide film formed by chemical vapor deposition.

[0037] According to the embodiment, the sidewalls of the control gate,the first insulating film, the floating gate and the tunnel oxide filmcan be favorably covered with the second insulating film.

BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The present invention will become more fully understood from thedetailed description given hereinbelow and the accompanying drawingswhich are given by way or illustration only, and thus are not limitativeof the present invention, and wherein:

[0039]FIG. 1A is a plane layout showing a virtual ground typenonvolatile semiconductor memory array to be manufactured, FIG. 1B is across sectional view taken along line X-X in FIG. 1A and FIG. 1C is across sectional view taken along line Y-Y in FIG. 1A;

[0040]FIG. 2 is an equivalent circuit diagram showing the abovenonvolatile semiconductor memory array;

[0041]FIGS. 3A to 3C are cross sectional views showing processes or amethod for manufacturing a nonvolatile semiconductor memory according toone embodiment of the invention;

[0042]FIGS. 4A to 4C are cross sectional views showing processes of themethod for manufacturing a nonvolatile semiconductor memory according tothe embodiment of the invention;

[0043]FIGS. 5A to 5D are cross sectional views showing processes of themethod for manufacturing a nonvolatile semiconductor memory according tothe embodiment of the invention;

[0044]FIG. 6 is a view for explaining actions in the method formanufacturing a nonvolatile semiconductor memory according to theembodiment of the invention;

[0045]FIG. 7 is a view for explaining a problem in a conventional methodfor manufacturing a nonvolatile semiconductor memory;

[0046]FIG. 8 is a view showing a threshold voltage distribution afterwrite in memory cells on the same word line in a nonvolatile memoryarray manufactured by the method for manufacturing a nonvolatilesemiconductor memory according to one embodiment of the invention;

[0047]FIG. 9 is a view showing a threshold voltage distribution afterwrite in memory cells on the same word line in a nonvolatile memoryarray manufactured by a conventional manufacturing method;

[0048]FIGS. 10A to 10C each are a cross sectional views showing aprocess of a conventional nonvolatile semiconductor memory;

[0049]FIGS. 11A to 11C are cross sectional views showing processes ofthe conventional method for manufacturing a nonvolatile semiconductormemory;

[0050]FIGS. 12A and 12B are cross sectional views showing processes ofthe conventional method for manufacturing a nonvolatile semiconductormemory; and

[0051]FIG. 13 is a cross sectional view showing a process of anotherconventional method for manufacturing a nonvolatile semiconductormemory.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0052] Hereafter, a method for manufacturing a nonvolatile semiconductormemory of the present invention is explained in detail with reference toan embodiment.

[0053]FIG. 1A is a plane layout showing a nonvolatile semiconductormemory array to be manufactured. FIG. 1B is a cross section taken alongline X-X in FIG. 1A. FIG. 1C is a cross section taken along line Y-Y inFIG. 1A. To make the explanation easy, the same component members as inFIGS. 10A through 12B are designated by the same reference numerals inthis embodiment.

[0054] This nonvolatile semiconductor memory array further has ahigh-concentration impurity diffusion layer 5 in a low-concentrationimpurity diffusion layer 4 formed in a surface of a semiconductorsubstrate 1. These impurity diffusion layers 4, 5 constitute asource/drain region i.e. a bit line. A tunnel oxide film 2, a floatinggate 3, a first insulating film 7 and a control gate 8 are successivelystacked on a channel region 19 between the source/drain regions 4, 5.Reference numeral 9 denotes an element separating impurity diffusionlayer. Reference numeral 10 denotes a second insulating film.

[0055] In this embodiment, there is explained a memory cell array of atype wherein source interconnect lines and drain interconnect lines arenot fixed and the source interconnect lines (ground interconnect lines)and the drain interconnect lines are appropriately switched(hereinafter, referred to as “virtual ground type”).

[0056] This nonvolatile semiconductor memory array is manufacturedaccording to a process order shown in FIGS. 3A to 3C and 4A to 4C. FIGS.3A to 3C snow cross sections of the nonvolatile semiconductor memoryarray in an X-X direction in course of manufacture. FIGS. 4A to 4C showcross sections thereof in a Y-Y direction.

[0057] First, as shown in FIG. 4A, a tunnel oxide film 2 having athickness of 10 nm is formed on a semiconductor substrate 1 composed ofsingle crystal silicon by thermal oxidation. Then, a first conductivelayer 3 having a thickness of 100 nm is deposited. The first conductivelayer 3 is composed of polysilicon as a material of a floating gate.Subsequently, as shown in FIG. 3A, the tunnel oxide film 2 and the firstconductive layer 3 are patterned in stripes extending in the Y-Ydirection. At this time, the size of the first conductive layer 3 in theX-X direction (channel direction) is set so as to match a size of thefloating gate to be finally formed.

[0058] Subsequently, phosphorus (P) ion implantation is performed underconditions of an acceleration energy of 50 keV and a dose of 3.0×10¹³ions/cm² by using the first conductive layer 3 patterned in stripes as amask so as to form an n-type low-concentration impurity diffusion layer4 in a region between the first conductive layers 3 in the surface ofthe semiconductor substrate 1.

[0059] Subsequently, photolithography is performed to form a photoresist(not shown) in stripes extending in the Y-Y direction. Arsenic (As) ionimplantation is performed by using this photoresist and the firstconductive layer 3 patterned in stripes as masks under conditions of anacceleration energy 15 keV and a dose of 4.5×10¹³ ions/cm² so as to forman n-type high-concentration impurity diffusion layer 5 in thelow-concentration impurity diffusion layer 4. These impurity diffusionlayers 4, 5 are used as a source/drain region i.e. a bit line.

[0060] Subsequently, as shown in FIG. 3B, an interlayer insulating film6 is deposited on these layers in a thickness exceeding the thickness ofthe first conductive layer 3 by the CVD method to sufficiently cover thefirst conductive layer 3. Subsequently, an etchback was performed toplanarize the surface of the interlayer insulating film 6 while theinterlayer insulating film 6 is so left as to be embedded between thefirst conductive layers 3.

[0061] Subsequently, as shown in FIGS. 3C and 4C, a first insulatingfilm 7 composed of e.g. an ONO film (oxide film/nitride film/oxide film)is deposited and then a second conductive layer 8 composed ofpolysilicon having a thickness of 200 nm is deposited. Then,photolithography is performed to form a photoresist (not shown) instripes extending in the X-X direction. The second conductive layer 8,the first insulating film 7 and the first conductive layer 3 are etchedand patterned by using this photoresist as a mask. Consequently, thereare formed a control gate 8 in stripes composed of the second conductivelayer, the first insulating film 7 in stripes composed of the ONO filmand a floating gate 3 in a rectangular solid composed of the firstconductive layer.

[0062] In this state, as shown in FIG. 5A which is an enlarged view of aportion P enclosed with a broken line in FIG. 4C, damages appears at aportion (shown with x) of the tunnel oxide film 2 immediately below asidewall of the floating gate 3. This damaged layer easily serves as apath for electrons to leak from the floating gate 3 to the semiconductorsubstrate 1 side during operation of a finished product. Accordingly, asshown in FIG. 5B, in order to remove the damaged portion of the tunneloxide film immediately below the sidewall of the floating gate 3,isotropic etching is performed. In this example, wet etching isperformed with use of fluorinated acid as an etchant so as to preciselyremove the damaged portion.

[0063] Subsequently, as shown in FIG. 5C as well as FIGS. 3C and 4C, asilicon oxide film having a thickness of 10 to 13 nm is deposited as asecond insulating film 10 or the semiconductor substrate 1 by ChemicalVapor Deposition (CVD). The silicon oxide film may be composed of an HTO(High Temperature chemical vapor deposition Oxide) film, for example.Consequently, sidewalls of the control gate 8, the first insulating film7, the floating gate 3 and the tunnel oxide film 2 are covered with thesecond insulating film 10. Since this second insulating film 10 isdeposited by CVD, the sidewalls of the control gate 8, the firstinsulating film 7, the floating gate 3 and the tunnel oxide film 2 canbe favorably covered.

[0064] Subsequently, as shown in FIG. 5D, thermal oxidation is performedin an oxygen atmosphere at e.g. 850° C. for 20 minutes so as to oxidizethe sidewalls of the floating gate 3 and the control gate 8 composed ofpolysilicon via the second insulating film 10. Consequently, a siliconoxide film 11 composed of polysilicon having a thickness of 20 to 30 nmis formed on sidewalls of the floating gate 3 and the control gate 8. Inthis case, as shown in FIG. 10A which is an enlarged view of a portionP2 enclosed with a broken line in FIG. 5C, oxidation of the grainboundary 13 between polysilicon grains 12 constituting the floating gate3 is suppressed and uniform oxidation occurs at the interface betweenthe floating gate 3 and its surrounding insulating films 10, 2.

[0065] Subsequently, boron (B) ion implantation is performed underconditions of an acceleration energy 40 keV and a dose 1.0×10¹³ ions/cm²by using the control gate 8 as a mask so as to form a p-type elementseparating impurity diffusion layer 9 in a surface region of thesemiconductor substrate 1 between the control gates 8, as shown in FIG.4C.

[0066] Then, an interlayer insulating film is deposited on this layer bya known method, a contact hole is opened in this interlayer insulatingfilm and then interconnect lines are further formed to complete anonvolatile memory, none of which are shown.

[0067]FIG. 2 shows an equivalent circuit of the nonvolatile memory arraymanufactured as described above.

[0068] Table 1 shows operation conditions in operations of write, eraseand read of data in the nonvolatile memory array when a memory cell C12(enclosed with broken line in FIG. 2) is selected. It is noted that therelationship among voltages in Table 1 is that VH1 and VH2 are higherthan Vcc, and that Vcc is higher than VL. TABLE 1 Word line Operationvoltage (V) Bit line voltage (V) mode WL1 WL2 BL1 BL2 BL3 BL4 Write −VH10 Float Vcc Float Float Erase VH2 VH2 or 0 0 0 0 0 Read Vcc 0 VL VL VLVL

[0069] In a write operation, a negative high voltage VH1 (for example,−8 V) is applied to a word line (control gate) WL1 connected to thememory cell C12. A prescribed positive power source voltage Vcc (forexample, 4 V) is applied to a bit line BL2 connected to a drain of thememory cell C12. Furthermore, the other bit lines BL1, BL3 and BL4 arein a floating state while the other word line WL2 has 0 V. Under theseconditions, in the memory cell C12, tunnel currents flow by an electricfield between the floating gate 3 and the drain 5 via the tunnel oxidefilm 2, so that data is written in the memory cell C12. Meanwhile, whena voltage is applied to the control gate 8 in a nonselected memory celle.g. a memory cell C11 wherein a source is connected to the bit lineBL2, tunneling between the source and the floating gate does not occur.This is because the source region is formed with an impurity diffusionlayer 4 having a low impurity concentration, and thus tunnel currents donot flow and data is not written.

[0070] In an erase operation, all the bit lines are set to be 0 V whilea positive high voltage VH2 (for example, 12 V) is applied to a desiredword line WL1. Consequently, written data in a plurality of memory cellsare erased in a batch. For example, when a voltage VH2 is applied to theword line WL1, written data in memory cells C11, C12 and C13 are erasedin a batch. When a voltage VH2 is applied to the word line WL2, writtendata of memory cells C21, C22 and C23 are erased in a batch.

[0071] In a read operation for reading the selected cell C12, aprescribed voltage Vcc (for example, 3 V) is applied to the word lineWL1 while a prescribed voltage VL (for example, 1 V) and 0 V are appliedto the bit line BL2 and the bit line BL3, respectively, to detectcurrents that flow between the bit lines.

[0072] It is noted that only the case where the memory cell C12 isselected is explained above, but data is simultaneously written toselected cells on the same word line.

[0073] In the above manufacturing method, as described above, isotropicetching is performed after the formation process of the floating gate 3so as to remove tho damaged portion of the tunnel oxide film 2immediately below the sidewall of the floating gate 3, which portionsare generated during the floating gate 3 formation process. Therefore,there is no path for electrons to leak from the floating gate 3 to thesemiconductor substrate 1 side during operation of a finished product.Furthermore, uniform oxidation occurs at the interface between thefloating gate 3 and the surrounding insulating films 10, 2 since thermaloxidation is performed after the deposition of the second insulatingfilm 10 to oxidize the sidewall of the floating gate 3 via the secondinsulating film 10. Therefore, equal FN (Fowler-Nordheim) currents flowthrough the tunnel oxide film 2 in each memory cell during a writeoperation. Thus, compared with a conventional memory, a variation inthreshold voltages among memory cells, for example, memory cells on thesame word line is reduced.

[0074] As a result, since threshold voltages do not vary on the sameword line, the number of steps during a write operation can be reduced,thereby shortening the write time.

[0075] Furthermore, memory cells affected by gate disturbance can bereduced since memory cells on the same word line wherein data isparticularly rapidly written can be erased.

[0076] Furthermore, miniaturization is not hindered since the secondinsulating film 10 is formed in a space portion of the floating gate 3.

[0077] Furthermore, the size of the floating gate 3 does not changeafter formation of the floating gate 3 depending on isotropic etching ofthe tunnel oxide film 2 or deposition of the second insulating film 10.Therefore, there is no problem of a short channel effect due to thechannel length or a narrow channel effect due to the channel width andno variation in threshold voltage attributable thereto occurs.

[0078]FIG. 8 shows a threshold voltage distribution after a writeoperation in memory cells on the same word line in the nonvolatilememory array manufactured by the above method. As evident in comparisonof FIG. 8 with FIG. 9 which shows the threshold voltage distribution inthe conventional nonvolatile memory array, variation in thresholdvoltages among memory cells on the same word line is reduced to 1.6 V inthe nonvolatile memory cell manufactured by the method of the presentembodiment.

[0079] In this embodiment, after the first conductive layer 3 isprocessed by using a mask in stripes extending in the X-X direction,isotropic etching of the tunnel oxide film 2 and deposition of thesecond insulating film 10 are performed by applying the presentinvention. However, the process order is not limited to this. After thefirst conductive layer 3 is processed by using a mask in stripesextending in the Y-Y direction, isotropic etching of the tunnel oxidefilm 2 and deposition of the second insulating film 10 may be performedby applying the present invention the present invention. This case canalso achieve a similar effect.

[0080] Furthermore, in this embodiment, a virtual ground type memorycell array suitable for high integration is manufactured, but the typeof the memory cell array is not limited to this type. The presentinvention is widely applied to other various types of nonvolatilesemiconductor memories.

[0081] The invention being thus described, it will be obvious that theinvention may be varied in many ways. Such variations are not beregarded as a departure from the spirit and scope of the invention, andall such modifications as would be obvious to one skilled in the art areintended to be included within the scope of the following claims.

What is claimed is:
 1. A method for manufacturing a nonvolatilesemiconductor memory wherein memory cells each having a tunnel oxidefilm, a floating gate, a first insulating film and a control gatestacked in this order are formed in a matrix on a semiconductorsubstrate, the method comprising the steps of: forming the tunnel oxidefilm on the semiconductor substrate; forming a first conductive layer tobe used as a material of the floating gate on the tunnel oxide film;patterning the first conductive layer in stripes extending in onedirection; forming a source/drain region in a surface of thesemiconductor substrate by using the first conductive layer as a mask;forming the first insulating film or the first conductive layer; forminga second conductive layer on the first insulating film; forming thecontrol gate in stripes composed of the second conductive layer, thefirst insulating film in stripes and the floating gate in a rectangularsolid composed of the first conductive layer by etching with a mask instripes extending a direction perpendicular to the first conductivelayer; removing a portion of the tunnel oxide film immediately below asidewall of the floating gate by isotropical etching; and depositing asecond insulating film on the control gate, sidewalls of the firstinsulating film, the floating gate and the tunnel oxide film to becovered with the second insulating film.
 2. The method for manufacturinga nonvolatile semiconductor memory according to claim 1, wherein afterthe second insulating film is deposited, thermal oxidation is performedto oxidize the sidewall of the floating gate via the second insulatingfilm.
 3. The method for manufacturing a nonvolatile semiconductor memoryaccording to claim 1, wherein isotropic etching of the tunnel oxide filmafter formation of the floating gate is performed by wet etching using afluorinated acid.
 4. The method for manufacturing a nonvolatilesemiconductor memory according to claim 1, wherein the second insulatingfilm is a silicon oxide film formed by chemical vapor deposition.